1. Field of the Invention
This invention relates to a memory system with a semiconductor memory device, specifically to an address management method of a flash memory storing eight value data.
2. Description of the Related Art
A NAND-type flash memory is known as an electrically rewritable and non-volatile semiconductor memory device (EEPROM). Recently, as the integration and capacity of the NAND-type flash memory increase, there is a great demand for recording moving image and the like in a video camera, a portable phone and the like.
As well known, the NAND-type flash memory may be erased only by an erase unit defined by a block. Conventionally, in a control system with a NAND-type flash memory, one or some physical blocks are defined as a logical block, and logic addresses are corresponded to the physical addresses.
To sequentially store moving images in a large logical space, it is usually used in a host device an allocation unit AU of, for example 4MByte, as a logical block unit. Conventionally, AU is defined by a capacity expressed by a power of two in consideration of its controllability.
In case a binary data storage scheme defined by 1-bit/cell or a four value data storage scheme defined by 2-bits/cell is used in the NAND-type flash memory, the physical block size serving as an erase unit may be expressed by a power of two (for example, refer to JP-A-2006-178923). However, in case an eight value data storage scheme defined by 3-bits/cell, the physical block size may not be expressed by a power of two, so that the logical block size in the host device is mismatched with the physical block size.
As a result, to continuously record moving images and the like, there are often generated copying operations in the flash memory, and it leads to reduction of the write performance.